1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a semiconductor device using a layer of material having a plurality of trenches formed therein and the resulting semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as FinFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D FinFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epi semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap F. The gate structure D is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D is the channel region of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins C in the source/drain regions of the device A is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions. Even if an epi “merger” process is not performed, an epi growth process will typically be performed on the fins C to increase their physical size. In the FinFET device A, the gate structure D may enclose both sides and the upper surface of all or a portion of the fins C to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer (not shown), e.g., silicon nitride, is positioned at the top of the fins C and the FinFET device only has a dual-gate structure (sidewalls only). The gate structures D for such FinFET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width (for a tri-gate device). Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
As device dimensions continue to shrink, the physical size of the fins (width and height) of a FinFET device are also reduced. As a result, the fins are very small structures in the world of semiconductor processing. Moreover, due to the prior art manner in which FinFET devices are made, the fins are subjected to numerous cleaning and etching processes that undesirably remove portions of the fin structures in the source/drain regions of the device despite best efforts to use highly selective etch/cleaning chemistries. Traditionally, the fins are the first components of a FinFET device that are formed. They are formed by performing an etching process through a patterned etch mask to define the fins in the substrate. Thereafter, a gate structure (either a final gate structure or a sacrificial gate structure) is formed above the channel region of the fins, by performing one or more reactive ion etching processes to pattern the gate materials and a gate cap layer. Thereafter, sidewall spacers are formed adjacent the gate structure by depositing a layer of spacer material and performing another reactive ion etching process to remove desired portions of the layer of spacer material, leaving sidewall spacers formed adjacent the gate structure. Later in the processing operation, an epi pre-clean process will be performed on the fins in the source/drain region of the device prior to forming an epi semiconductor material on the fins in the source/drain regions. From the brief explanation above, the fins in the source/drain regions are subjected to at least two reactive ion etching processes (gate patterning and spacer formation), as well as the epi pre-clean process, all of which tend to undesirably remove fin material.
In some cases, damage to the fin structures in the source/drain regions of the device may not be a significant concern, i.e., an application in which there may be significant growth of epi material in the source/drain regions. Nevertheless, even in those situations, problems can occur if too much of the epi material is grown in the source/drain regions of the device, e.g., epi-to-epi shorting between adjacent devices or around the end of the gate structure on a single device.
Another area of potential concern is related to the formation of so-called self-aligned contacts. The typical process flow for forming such contacts involves forming an opening in a layer of silicon dioxide that is supposed to stop on a silicon nitride gate cap layer and a silicon nitride sidewall spacer (that are formed to protect the gate materials). Unfortunately, there is a risk of consuming too much of the gate cap layer and/or the sidewall spacer during the contact opening etching process which can lead to exposure of the gate materials. When the contact is formed in the contact opening, there is a chance of creating a contact-to-gate electrical short due to the loss of the cap and/or spacer material.
FIG. 1B is a simplistic plan view of an illustrative transistor device (which can be either a planar or FinFET device). As depicted, the transistor is comprised of source and drain regions that are formed in an active region surrounded by isolation material, typically silicon dioxide. The gate structure (“gate”) of the device is formed above the active region and one or more sidewall spacers are formed adjacent the gate structure using a variety of known processing techniques. Typically the spacers are formed by conformably depositing a layer of spacer material, e.g., silicon nitride, and thereafter performing an anisotropic etching process. Note that the spacer is formed around the entire perimeter of the gate structure and that the spacer is formed with the intent that it has a substantially uniform thickness at all locations around the perimeter of the gate structure.
The present disclosure is directed to various methods of forming a semiconductor device using a layer of material having a plurality of trenches formed therein and the resulting semiconductor device that may avoid, or at least reduce, the effects of one or more of the problems identified above.